This invention relates generally to junction solar cell structures, and more particularly to a floating emitter solar cell.
There is continuing need to improve the conversion efficiency of solar cells. Since about 1956, silicon solar cell conversion efficiency has been improved from about 5% to more than 16%. Improvements both in materials and in processing technologies, resulting in shallower junctions and lower series resistance, has been largely responsible for this improvement. However, a compromise between shallower junctions and lower series resistance of the front diffused region soon reached its limits. Similarly, a compromise between more absorption with thicker cells and more collection at the front junction, which need longer minority carrier diffusion length, has reached its limit.
The quest for higher efficiency has led to multijunction solar cells, such as tandem (stacked) junction solar cells. Because of improvements in techniques of epitaxial silicon growth, with finer control of doping possible, a multilayered structure of two or more p/n junctions can be produced with n.sup.+ /p.sup.+ tunnel junctions between them acting as low resistance connections. The stack is characterized by a high open circuit voltage that is the sum of the open circuit voltages of the individual cells. The problem is that a large interface recombination velocity (10.sup.5 cm/sec) at the tunnel junction of a multijunction silicon solar cell degrades its performance below that of a conventional monojunction silicon solar cell. Consequently, such tandem solar cells affect efficiency of the cells. Improvement is necessary if efficiencies of over 20% (AM1) are to be achieved with high open circuit voltages.
More recent developments have led to floating emitter solar cells. See U.S. Pat. No. 4,133,698 to Shang-Yi Chiang and Bernard G. Carbajal, and a later paper by Matzen, Chiang, and Carbajal titled "A Device Model for the Tandem Junction Solar Cell" published in IEEE Transactions on Electron Devices, Vol. ED-26(9) pp. 1365-1368, September 1979; and U.S. Pat. No. 4,341,918 to John C. Evans, An-Ti Chai and Chandra P. Goradia, and a later paper titled "High-Voltage Solar-Cell Chip" by V. J. Kapoor, G. J. Valco, G. G. Skebe and J. C. Evans, Jr. published in the Journal of Applied Physics, Vol. 57(4), pp 1343-1346, Feb. 15, 1985. An advantage of a solar cell structure having a floating emitter is that the efficiency of the cell is less sensitive to surface and bulk recombination losses in the front junction emitter layer.
The inventors herein, have conducted minority carrier recombination rate studies and explored the barriers to achieving high efficiency solar cells. They studied a simple vertical floating emitter structure for a solar cell to attain very high efficiency above 20% (AM1). This structure was disclosed in the Progress Report 23 (September 1983 to March 1984) of the Flat-Plate Solar Array Project (J.P.L. Publication 84-47), that was prepared for the U.S. Department of Energy through an Agreement with National Aeronautics and Space Administration by the Jet Propulsion Laboratory, California Institute of Technology. It will be described hereinafter with reference to FIGS. 1a and 1b in conjunction with an equivalent circuit diagram shown in FIG. 2. A two-junction solar cell using the transistor action similar to that disclosed by Evans, et al., in U.S. Pat. No. 4,341,918 will be described.
The earlier U.S. Pat. No. 4,133,698 discloses a two-junction solar cell using transistor action. Although that patent does not seem to recognize the importance of the transistor action, the later paper by Matzen, Chiang, and Carbajal referred to above does recognize it, and gives the correct theory of operation using a simple equivalent circuit.
All of the prior art structures are back surface contact solar cell "transistors" having both base and collector contacts on the back. An object of this invention is to provide a high efficiency floating emitter solar cell "transistor" of a configuration which uses a front surface contact for one of the two contacts required for the base and collector.
Still another object is to provide floating emitter solar cell "transistors" of such a configuration that they may be easily fabricated with standard VLSI techniques.
Yet another object is to provide floating emitter solar cell "transistors" that may be fabricated with a thick substrate layer so that mechanical breakage problems for large (4 to 6 inch diameter) cells are avoided.